R&D (FilterCavity)
NaokiAritomi - 23:57, Wednesday 13 February 2019 (1211)
Locking of ML-CC PLL with both fast and slow loop at 7 MHz
 
[Aritomi, Yuhang, Marco, Matteo]
 
We succeeded in locking ML-CC PLL with both fast and slow loop at 7 MHz. First attached picture shows spectrum of locked beat note. It's very stable with slow loop.
Note that an integrator for slow loop must be turned on a few seconds before slow loop is turned on.
 
Reduction of EOM sideband for SHG and IRMC
We found that EOM sideband for SHG and IRMC (15.2 MHz) could be a problem for locking PLL at 7 MHz since lower sideband of 7 MHz beat note appears at 15.2-7 = 8.2 MHz, which is close to 7 MHz. So we reduced EOM sideband for SHG and IRMC by adding 12 dB attenuator to 20.8 dB RF amplifier, which corresponds to 20.8-12=8.8 dB amplification for sideband.
We also checked  the sidebands without sideband amplification (0 dB). Second, third and fourth attached pictures show beat note at 30 MHz and its sidebands at 14.8 MHz and 45.2 MHz when sideband amplification is 20.8 dB, 8.8 dB, 0 dB. Amplitude of beat note and sidebands are as follows.
 

It's very stable with slow loop.
First attached picture shows spectrum of locked beat note. 
       
       
       
       
       
       
       
       
Note that an integrator for slow loop must be turned on a few seconds before slow loop is turned on.
sideband amplification
    20.8 dB
     8.8 dB
     0 dB
beat note
   -38 dBm
   -38 dBm
   -38 dBm
lower sideband
   -45 dBm
   -52 dBm
   -66 dBm
upper sideband
   -55 dBm
   -60 dBm
         -

We can lock SHG with both 8.8 dB and 0 dB amplification, but SHG locking is not good for 0 dB amplification. So we decided to use 8.8 dB amplification.

Images attached to this report
1211_20190213155613_7mhz.jpg 1211_20190213155653_8db.jpg 1211_20190213155708_8db.jpg 1211_20190213155722_0db.jpg