In elog1727, I tuned CC PLL frequency from the fitting of CC separation frequency and CC PLL frequency, but the error of the fitting parameters is quite large with respect to optimal CC separation frequency 108 Hz. So this method is not precise to decide the correct detuning.
As written in elog2294, current CCFC error signal is not consistent with theoretical plot with optimal detuning, but instead it is similar to the theoretical plot with 25 Hz detuning.
If the current detuning is 25 Hz, we have to change the detuning by 29 Hz to obtain optimal detuning 54 Hz. Using the formula in elog1727, the CC PLL frequency has to be changed by 2*29 Hz/1.907605 = 30.41 Hz. Since the current CC PLL frequency is 6.99704303 MHz, optimal CC PLL frequency should be either 6.99707344 MHz or 6.99701262 MHz. I checked both cases by looking at CCFC error signal and found that 6.99701262 MHz is correct one (In DDS, 6.99701253 MHz was set).
Here is the new CC PLL setting. I saved this setting as 20201126_dds3_CCFC.
| channel | function | frequency (MHz) | binary number |
| CH0 | CC PLL | 20.99103760 | 1010 10111111 01010110 01011000 |
| CH2/3 | CC1/CCFC demod | 13.99402518 | 111 00101010 00111001 10010000 |
| 6.99701253 | 11 10010101 00011100 11001000 |
Attached plot shows CCFC error signal with different CCFC demodulation phase. Amplitude of the CCFC error signal is normalized with 83mV which is the amplitude of CCFC error signal when CCSB are off resonance of FC and CC1 is scanned.
Now the shape of CCFC error signal is similar to theoretical plot. In addtion to that, zero crossing point of blue curve in second plot is around 58Hz which is almost optimal detuning.
